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summit microelectronics, inc. ? 300 orchard city drive, suite 131 campbell, ca 95008 telephone 408-378- 6461 fax 408-378-6586 www.summitmicro.com 1 s93wd662/s93wd663 ? summit microelectronics, inc. 2000 2013 2.0 3/21/00 characteristics subject to change without notice precision supply-voltage monitor and reset controller with a watchdog timer and 4k-bit microwire memory summit microelectronics, inc. features ? precision monitor & reset controller ? reset and reset# outputs ? guaranteed reset assertion to v cc = 1v ? 200ms reset pulse width ? internal 1.26v reference with 1% accuracy ? zero external components required watchdog timer ? nominal 1.6 second time-out period ? reset by any transition of cs memory ? 4k-bit microwire memory ? s93wd662 ? internally ties org low ? 100% compatible with all 8-bit implementations ? sixteen byte page write capability ? s93wd663 ? internally ties org high ? 100% compatible with all 16-bit implementations ? eight word page write capability overview the s93wd662 and s93wd663 are precision power supervisory circuits providing both active high and active low reset outputs. both devices incorporate a watchdog timer with a nominal time-out value of 1.6 seconds. both devices have 4k-bits of e 2 prom memory that is accessible via the industry standard microwire bus. the s93wd662 is configured with an internal org pin tied low providing a 8-bit byte organization and the s93wd663 is configured with an internal org pin tied high providing a 16-bit word organization. both the s93wd662 and s93wd663 have page write capabil- ity. the devices are designed for a minimum 100,000 program/erase cycles and have data retention in ex- cess of 100 years. block diagram + ? gnd v cc 8 5 reset# 6 v trip reset pulse generator 5khz oscillator reset control mode decode address decoder write control data i/o e 2 prom memory array reset 7 1.26v sk 2 di 3 watchdog timer cs 1 2013 t bd 2.0
2 s93wd662/s93wd663 2013 2.0 3/21/00 pin functions pin name function cs chip select sk clock input di serial data input do serial data output v cc +2.7 to 6.0v power supply gnd ground reset/reset# reset i/o pin configuration device operation applications the s93wd662/wd663 is ideal for applications requir- ing low voltage and low power consumption. this device provides microcontroller reset control and can be manually resettable. reset controller description the s93wd662/wd663 provides a precision reset con- troller that ensures correct system operation during brownout and power-up/-down conditions. it is config- ured with two open drain reset outputs: pin 7 is an active high output and pin 6 is an active low output. during power-up, the reset outputs remain active until v cc reaches the v trip threshold. the outputs will con- tinue to be driven for approximately 200ms after reach- ing v trip . the reset outputs will be valid so long as v cc is 1.0v. during power-down, the reset outputs will begin driving active when v cc falls below v trip . the reset pins are i/os; therefore, the s93wd662/ wd663 can act as a stabilization circuit for an externally applied reset. the inputs are edge triggered; that is, the reset input will initiate a reset time-out after detecting a low to high transition and the reset# input will initiate a reset time-out after detecting a high to low transition. refer to the applications information section for more details on device operation as a debounce/reset ex- tender circuit. it should be noted the reset outputs are open drain. when used as outputs driving a circuit they need to be either tied high (reset#) or tied to ground (reset) through the use of pull-up or pull-down resistors. refer to the applications aid section for help in determining the value of resistor to be used. internally these pins are weakly pulled up (reset#) and pulled down (reset). if the signals are not being used the pins may be left unconnected. watchdog timer description the s93wd662/wd663 has a watchdog timer with a nominal time-out period of 1.6 seconds. whenever the watchdog times out, it will generate a reset output to both pins 6 and 7. the watchdog timer is reset by any transition on cs. the watchdog timer will be held in a reset state during power-on while v cc is less than v trip . once v cc ex- ceeds v trip the watchdog will continue to be held in a reset state for the t purst period. after t purst it will be released and the timer will begin operation. if either reset input is asserted the watchdog timer will be reset and remain in the reset condition until either t purst has expired or the reset input is released, whichever is longer. general operation the s93wd662/wd663 is a 4096-bit nonvolatile memory intended for use with industry standard microproces- sors. the s93wd663 is organized as x16, seven 11-bit instructions control the reading, writing and erase op- erations of the device. the s93wd662 is organized as x8, seven 12-bit instructions control the reading, writing and erase operations of the device. the device operates on a single 3v or 5v supply and will generate on chip, the high voltage required during any write operation. instructions, addresses, and write data are clocked into the di pin on the rising edge of the clock (sk). the do pin is normally in a high impedance state except when reading data from the device, or when checking the ready/busy status after a write operation. cs sk di do v cc reset reset# gnd 1 2 3 4 8 7 6 5 8-pin pdip or 8-pin soic 2014 t pcon 2.0
3 s93wd662/s93wd663 2013 2.0 3/21/00 sk 2013 ill 3 1.0 di cs do t dis t pd0, t pd1 t csmin t css t dis t dih t skhi t csh valid valid data v alid t sklow the ready/busy status can be determined after the start of a write operation by selecting the device (cs high) and polling the do pin; do low indicates that the write operation is not completed, while do high indicates that the device is ready for the next instruction. see the applications aid section for detailed use of the ready busy status. the format for all instructions is: one start bit; two op code bits and either eight (x16) or nine (x8) address or instruction bits. read upon receiving a read command and an address (clocked into the di pin), the do pin of the s93wd662/ wd663 will come out of the high impedance state and, will first output an initial dummy zero bit, then begin shifting out the data addressed (msb first). the output data bits will toggle on the rising edge of the sk clock and are stable after the specified time delay (t pd0 or t pd1 ). write after receiving a write command, address and the data, the cs (chip select) pin must be deselected for a minimum of 250ns (t csmin ). the falling edge of cs will start automatic erase and write cycle to the memory location specified in the instruction. the ready/busy status of the s93wd662/wd663 can be determined by selecting the device and polling the do pin. erase upon receiving an erase command and address, the cs (chip select) pin must be deselected for a minimum of 250ns (t csmin ). the falling edge of cs will start the auto erase cycle of the selected memory location. the ready/busy status of the s93wd662/wd663 can be figure 1. sychronous data timing figure 2. read instruction timing sk 2013 ill4 1.0 cs di do t cs standby t hz high-z high-z 11 0 a n a n ? 1 a 0 0 d n d n ? 1 d 1 d 0 t pd0
4 s93wd662/s93wd663 2013 2.0 3/21/00 determined by selecting the device and polling the do pin. once cleared, the content of a cleared location returns to a logical ? 1 ? state. erase/write enable and disable the s93wd662/wd663 powers up in the write disable state. any writing after power-up or after an ewds (write disable) instruction must first be preceded by the ewen (write enable) instruction. once the write in- struction is enabled, it will remain enabled until power to the device is removed, or the ewds instruction is sent. the ewds instruction can be used to disable all s93wd662/wd663 write and clear instructions, and will prevent any accidental writing or clearing of the device. data can be read normally from the device regardless of the write enable/disable status. erase all upon receiving an eral command, the cs (chip se- lect) pin must be deselected for a minimum of 250ns (t csmin ). the falling edge of cs will start the self clocking clear cycle of all memory locations in the device. the clocking of the sk pin is not necessary after the device has entered the self clocking mode. the ready/busy status of the s93wd662/wd663 can be determined by selecting the device and polling the do pin. once cleared, the contents of all memory bits return to a logical ? 1 ? state. write all upon receiving a wral command and data, the cs (chip select) pin must be deselected for a minimum of 250ns (t csmin ). the falling edge of cs will start the self clocking data write to all memory locations in the device. the clocking of the sk pin is not necessary after the device has entered the self clocking mode. the ready/ busy status of the s93wd662/wd663 can be deter- mined by selecting the device and polling the do pin. it is not necessary for all memory locations to be cleared before the wral command is executed. page write 93wd662 - assume wen has been issued. the host will then take cs high, and begin clocking in the start bit, write command and 9-bit byte address immediately followed by the first byte of data to be written. the host can then continue clocking in 8-bit bytes of data with each byte to be written to the next higher address. internally the address pointer is incremented after receiving each group of eight clocks; however, once the address counter reaches x xxxx 1111 it will roll over to x xxxx 0000 with the next clock. after the last bit is clocked in no internal write operation will occur until cs is brought low. 93wd663 - assume wen has been issued. the host will then take cs high, and begin clocking in the start bit, write command and 8-bit byte address immediately followed by the first 16-bit word of data to be written. the host can then continue clocking in 16-bit words of data with each word to be written to the next higher address. internally the address pointer is incremented after receiving each group of sixteen clocks; however, once the address counter reaches xxxx x111 it will roll over to xxxx x000 with the next clock. after the last bit is clocked in no internal write operation will occur until cs is brought low. continuous read this begins just like a standard read with the host issuing a read instruction and clocking out the data byte [word]. if the host then keeps cs high and continues generating clocks on sk, the s93wd662/ wd663 will output data from the next higher address location. the s93wd662/wd663 will continue incrementing the address and outputting data so long as cs stays high. if the highest address is reached, the address counter will roll over to address 0000. . cs going low will reset the instruction register and any subsequent read must be initiated in the normal manner of issuing the command and address.
5 s93wd662/s93wd663 2013 2.0 3/21/00 figure 3. write instruction timing figure 4. erase instruction timing figure 5. ewen/ewds instruction timing sk 2013 ill 5 1.0 cs di do t cs standby high-z high-z 101 a n a n-1 a 0 d n d 0 busy ready status verify t sv t hz t ew sk 2013 ill6 1.0 cs di do standby high-z high-z 1 a n a n-1 busy ready status verify t sv t hz t ew t cs 11 a 0 sk 2013 ill 7 1.0 cs di standby 10 0 * * enable=1 1 disable=00
6 s93wd662/s93wd663 2013 2.0 3/21/00 figure 7. wral instruction timing sk 2013 ill 10 1.0 cs di do t cs high-z 10 1 busy ready status verify t sv t hz t ew 0 0 standby d o d n instruction set instruction start opcode address data comments bit x8 x16 x8 x16 read 1 10 a8 ? a0 a7 ? a0 read address an ? a0 erase 1 11 a8 ? a0 a7 ? a0 clear address an ? a0 write 1 01 a8 ? a0 a7 ? a0 d7 ? d0 d15 ? d0 write address an ? a0 ewen 1 00 11xxx xxxx 11xxx xxx write enable ewds 1 00 00xxx xxxx 00xxx xxx write disable eral 1 00 10xxx xxxx 10xxx xxx clear all addresses wral 1 00 01xxx xxxx 01xxx xxx d7 ? d0 d15 ? d0 write all addresses 2013 pgm t5 1.1 figure 6. eral instruction timing sk 2013 ill 8 1.0 cs di do t cs high-z high-z 10 1 busy ready status verify t sv t hz t ew 00 standby
7 s93wd662/s93wd663 2013 2.0 3/21/00 absolute maximum ratings* temperature under bias ......................................................................................................... ........................... ? 55 c to +125 c storage temperature ............................................................................................................ ............................. ? 65 c to +150 c voltage on any pin with respect to ground (1) ............................................................................................. ? 2.0v to +v cc +2.0v v cc with respect to ground ........................................................................................................ .......................... ? 2.0v to +7.0v package power dissipation capability (ta = 25 c) ............................................................................................................. 1.0w lead soldering temperature (10 secs) ........................................................................................... ................................... 300 c output short circuit current (2) ............................................................................................................................... ............ 100 ma *comment stresses above those listed under ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specificat ion is not implied. exposure to any absolute maximum rating for extended periods may affect device performance and reliability. note: (1) the minimum dc input voltage is ? 0.5v. during transitions, inputs may undershoot to ? 2.0v for periods of less than 20 ns. maximum dc voltage on output pins is v cc +0.5v, which may overshoot to v cc +2.0v for periods of less than 20 ns. (2) output shorted for no more than one second. no more than one output shorted at a time. (3) this parameter is tested initially and after a design or process change that affects the parameter. (4) latch-up protection is provided for stresses up to 100 ma on address and data pins from ? 1v to v cc +1v. d.c. operating characteristics (over recommended operating conditions unless otherwise specified) limits symbol parameter min. typ. max. units test conditions i cc power supply current 3 ma di = 0.0v, f sk = 1mhz (operating) v cc = 5.0v, cs = 5.0v, output open i sb power supply current 50 a cs = 0v (standby) reset outputs open i li input leakage current 2 a v in = 0v to v cc i lo output leakage current 10 a v out = 0v to v cc , (including org pin) cs = 0v v il1 input low voltage -0.1 0.8 v 4.5v-v cc <5.5v v ih1 input high voltage 2 v cc +1 v v il2 input low voltage 0 v cc x0.2 v 1.8v-v cc <2.7v v ih2 input high voltage v cc x0.7 v cc +1 v v ol1 output low voltage 0.4 v 4.5v-v cc <5.5v v oh1 output high voltage 2.4 v i ol = 2.1ma i oh = -400a v ol2 output low voltage 0.2 v 1.8v-v cc <2.7v v oh2 output high voltage v cc -0.2 v i ol = 1ma i oh = -100a 2013 pgm t3 1.1 temperature min max commercial 0 c +70 c industrial -40 c +85 c recommended operating conditions 2013 pgm t7 1.0 reliability characteristics symbol parameter min. max. units n end (3) endurance 100,000 cycles/byte t dr (3) data retention 100 years v zap (3) esd susceptibility 2000 volts i lth (3)(4) latch-up 100 ma 2013 pgm t2 1.1
8 s93wd662/s93wd663 2013 2.0 3/21/00 limits v cc =2.7v-4.5v v cc =4.5v-5.5v test symbol parameter min. max. min. max. units conditions t css cs setup time 100 50 ns t csh cs hold time 0 0 ns v il = 0.45v t dis di setup time 200 100 ns v ih = 2.4v t dih di hold time 200 100 ns c l = 100pf t pd1 output delay to 1 0.5 0.25 s v ol = 0.8v t pd0 output delay to 0 0.5 0.25 s v oh = 2.0v t hz (1) output delay to high-z 200 100 ns t ew program/erase pulse width 10 10 ms t csmin minimum cs low time 0.5 0.25 s t skhi minimum sk high time 0.5 0.25 s t sklow minimum sk low time 0.5 0.25 s t sv output delay to status valid 0.5 0.25 s c l = 100pf sk max maximum clock frequency dc 500 dc 1000 khz note: (1) this parameter is tested initially and after a design or process change that affects the parameter. note: (1) this parameter is tested initially and after a design or process change that affects the parameter. pin capacitance symbol test max. units conditions c out (1) output capacitance (do) 5 pf v out =ov c in (1) input capacitance (cs, sk, di, org) 5 pf v in =ov 2013 pgm t4 1.0 a.c. characteristics (over recommended operating conditions unless otherwise specified) c l = 100pf 2013 pgm t6 1.0
9 s93wd662/s93wd663 2013 2.0 3/21/00 figure 8. reset timing diagram reset circuit ac and dc electrical characteristics 2.7 5 volt-a 5 volt-b symbol parameter min max min max min max unit v trip reset trip point 2.55 2.7 4.25 4.5 4.50 4.75 v t purst power-up reset timeout 130 270 130 270 130 270 ms t rpd v trip to reset output delay 5 5 5 s v rvalid reset# output valid 1 1 1 v t glitch glitch reject pulse width 30 30 30 ns v olrs reset output low voltage i ol =1ma 0.4 0.4 0.4 v v ohrs reset# output high i oh v cc -.75 v cc -.75 v cc -.75 v 2013 pgm t1 1.1 v cc v rvalid v trip t purst reset# reset 2013 t fig08 2.0 t glitch t rpd t purst t rpd
10 s93wd662/s93wd663 2013 2.0 3/21/00 .228 (5.80) .244 (6.20) .016 (.40) .035 (.90) .020 (.50) .010 (.25) x45 .0192 (.49) .0138 (.35) .061 (1.75) .053 (1.35) .0098 (.25) .004 (.127) .05 (1.27) typ. .275 (6.99) typ. .030 (.762) typ. 8 places .050 (1.27) typ. .050 (1.270) typ. 8 places .157 (4.00) .150 (3.80) .196 (5.00) 1 .189 (4.80) footprint 8pn jedec soic ill.2 .375 (9.525) pin 1 indicator .015 (.381) min. .130 (3.302) .100 (2.54) typ. .018 (.457) typ. .060 .005 (1.524) .127 typ. .130 (3.302) seating plane .070 (1.778) .0375 (0.952) .300 (7.620) 5 -7 typ. (4 plcs) .350 (8.89) .009 .002 (.229 .051) 0 -15 .250 (6.350) 8pn pdip/p ill.3 8 pin soic (type s) package jedec (150 mil body width) 8 pin pdip (type p) package
11 s93wd662/s93wd663 2013 2.0 3/21/00 frequently the reset controller will be deployed on a pc board that provides a peripheral function to a system. examples might be modem or network cards in a pc or a pcmcia card in a laptop. in instances like this the peripheral card may have a requirement for a clean reset function to insure proper operation. the system may or may not provide a reset pulse of sufficient duration to clear the peripheral or to protect data stored in a nonvolatile memory. the i/o capability of the reset pins can provide a solution. the system ? s reset signal to the peripheral can be fed into the s93wd662/wd663 and it in turn can clean up the signal and provide a known entity to the peripheral ? s circuits. the figure below shows the basic timing characteristics under the assumption the reset input is shorter in duration than t purst . the same reset output affect can be attained by using the active high reset input. when planning your resistor pull-up and pull-down values, use the following chart to help determine min. resistances. condition min typ max units v cc = 1.0v, i ol =100a 0.3 v v cc = 1.2v, i ol =100a 0.3 v v cc = 3.0v, i ol =500a 0.3 v v cc = 3.6v, i ol =500a 0.3 v v cc = 4.5v, i ol =750a 0.3 v v cc = 1.0v, i ol =100a 0.4 v v cc = 1.2v, i ol =150a 0.4 v v cc = 3.0v, i ol =750a 0.4 v v cc = 3.6v, i ol =1ma 0.4 v v cc = 4.5v, i ol =1ma 0.4 v v cc = 1.0v, i oh =400a v cc -0.75 v v cc = 1.2v, i oh =800a v cc -0.75 v v cc = 3.0v, i oh =800a v cc -0.5 v v cc = 3.6v, i oh =800a v cc -0.5 v v cc = 4.5v, i oh =800a v cc -0.5 v worst case reset sink/source capabilities at various v cc levels parameter symbol reset# output v ol voltage reset# output v ol voltage reset output v oh voltage 2013 pgm t5 1.0 reset# input reset# output reset output 2013 t fig09 2.0 t purst
12 s93wd662/s93wd663 2013 2.0 3/21/00 ready/busy status ready/busy status ready/busy status ready/busy status ready/busy status during the internal write operation the s93wd662/wd663 memory array is inaccessible. after starting the write operation (taking cs low) the host can implement a 10ms time-out routine or alternatively it can employ a polling routine that tests the state of the do pin. after starting the write, testing for the status is easily accomplished by taking cs high and testing the state of do. if it is low the device is still busy with the internal write. if it is high the write operation has completed. for the polling routine the host has the option of toggling cs for each test of do, or it can place cs high and then intermittently test do. sk is not required for any of these operations. once the device is ready, it will continue to drive do high whenever the s93wd662/wd663 is selected. the ready state of do can be cleared by clocking in a start bit; this start bit can either be the beginning of a new command sequence or it can be a dummy start bit with cs returning low before the host issues a new command. sk 2013 ill 13 1.0 cs di do t cs high-z high-z status cleared busy ready status verify t sv t hz t ew
13 s93wd662/s93wd663 2013 2.0 3/21/00 ordering information ordering information ordering information ordering information ordering information s93wd663 base part number s93wd663 = 16-bit configuration s93wd662 = 8-bit configuration tape and reel option blank = tube t = tape and reel package p = 8 lead pdip s = 8 lead 150mil soic operating voltage range a = 4.5v to 5.5v v trip min. @ 4.25v b = 4.5v to 5.5v v trip min. @ 4.50v 2.7 = 2.7v to 5.5v v trip min. @ 2.55v p -2.7 t 2012 ill11 1.1
14 s93wd662/s93wd663 2013 2.0 3/21/00 notice summit microelectronics, inc. reserves the right to make changes to the products contained in this publication in order to impr ove design, performance or reliability. summit microelectronics, inc. assumes no responsibility for the use of any circuits describ ed herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user?s specific application. while the information in this publication has been carefully checked, summit microelectronics, i nc. shall not be liable for any damages arising as a result of any error or omission. summit microelectronics, inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect it s safety or effectiveness. products are not authorized for use in such applications unless summit microelectronics, inc. receives writte n assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks ; and (c) potential liability of summit microelectronics, inc. is adequately protected under the circumstances. ? copyright 2000 summit microelectronics, inc.

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